1. Field of the Invention
The present invention relates to graphics controllers in general and in particular to a method and apparatus comprising a graphics controller having the capacity for translating X and Y array addresses of words in a bit map into corresponding physical row and column addresses of the words in memory chips without the need for an intermediate linear address, for selectively addressing either 16 bit words or 1 bit words in the bit map and for refreshing a video monitor using bit aligned, as distinguished from word aligned, video screen and window data.
2. Description of Prior Art
Video systems comprise graphics controllers and video monitors. In a typical graphics controller there are provided a bit map, a circuit for storing video data in the bit map and a circuit for reading the video data from the bit map onto a video monitor. The operations which take place during the storing of the data in the bit map and the reading of the data from the bit map to the video monitor take place in what are commonly called memory update and video monitor refresh modes, respectively.
A typical bit map may be thought of as a large array of memory locations comprising a plurality of multi-bit words. For example, a 4K.times.4K bit map of 16-bit words comprises a total of over one million words with 256 words in each row of the bit map. The location of each word in the bit map is identified by an X and a Y logical or array address.
In practice, the bit map actually comprises a plurality of memory chips. For example, a typical memory chip may comprise 1K.times.1K storage locations. Therefore, if 1K.times.1K memory chips are used, 16 such memory chips are required to store one million 16-bit words. The location of each bit in the memory chip is identified by a row and a column physical address conveniently called RAD and CAD, respectively.
From the above discussion it is evident that in order to address a bit in a memory chip using the logical address of the word in the bit map, it is necessary to generate a row and a column address of the bit in the memory chip from the logical address of the word in the bit map. This is done by translating the X and Y array or logical address of the word in the bit map into a corresponding row and column physical address in the memory chip.
Heretofore, the apparatus required for translating logical addresses of a word in a bit map to corresponding physical addresses of the bit in a memory chip comprised a graphics controller and a random access memory (RAM) controller. In practice, the RAM controller typically comprised a table look-up memory and an address sequencer.
In operation, the graphics controller was provided with the X and Y logical addresses of data words in a bit map and the width of the rows as measured in words in the X direction in the memory chips. From this information, the graphics controller generated corresponding linear addresses as follows: EQU Linear Address=Y.times.width+X
The linear addresses thus generated were then sent to the RAM controller where they were used to generate corresponding row and column physical addresses as well as chip select signals.
The prior art method of generating row and column physical addresses and chip select signals was costly not only in terms of the time it took to perform the computations, i.e. the product and sums, necessary to generate the linear addresses, but it was also costly in that it required a separate apparatus, i.e. the RAM controller.
Another disadvantage of the prior art methods and apparatus for addressing a video memory was that no means was provided for addressing individual bits within a word in the bit map. Heretofore, in order to modify one or more individual bits within a word, it was necessary to read the entire word, modify the desired bit(s) and rewrite the word to the memory. As a result, the modification of individual bits within a word, which is often required when modifying lines and curves on a video display, was very time consuming.
Typically, the number of bits in a bit map in a video system far exceeds the number of pixels on the monitor screen in the system. As a consequence, when video data is presented on the screen, it is taken from only a portion of the bit map. For example, when writing to the screen there are provided a starting address X.sub.S,Y.sub.S and an ending address X.sub.E,Y.sub.E which correspond to and identify a block of words in the bit map to be displayed on the screen. The data thus identified is then scanned and written to the screen.
At times, a portion or a section, i.e. window, of a screen of video data is replaced with other data. The replaced window is called an apparent window and is identified by the starting and ending addresses X.sub.AS,Y.sub.AS and X.sub.AE,Y.sub.AE of words in the bit map, respectively. The replacing window is called a real window and is identified by the starting and ending addresses X.sub.RS,Y.sub.RS and X.sub.RE,Y.sub.RE of words in the bit map, respectively.
In operation, the data in the bit map to be displayed on the screen is scanned in a regular fashion one line at a time as the physical addresses are generated from the logical addresses. When the address generating apparatus encounters the starting address of an apparent window, it substitutes for the apparent window the data identified by the real addresses X.sub.RS,Y.sub.RS, X.sub.RE and Y.sub.RE.
Heretofore, the methods and apparatus used for displaying bit map data on a screen and for substituting real window data for apparent window data generally has been restricted to word aligned screens and windows. As a consequence, the first and last bit in each uninterrupted portion of a line of data displayed on a screen or in a window has had to correspond to the first and last bit of a word in the bit map. Such a limitation is a significant restriction on the resolution of a video system.